-------------------------------------------------------------------------------- Matrox Imaging Library (MIL) 8.0 Update 8 MilSolios.txt February 26, 2007 Copyright© 2007 by Matrox Electronic Systems Ltd. All rights reserved. -------------------------------------------------------------------------------- This document outlines what is new with MIL for Matrox Solios and explains the current limitations and particularities when using MIL with Matrox Solios. It also presents last minute information that did not make it into the manual or on-line help. Note that this text file serves to complement your manual. The information found in this file overrides your formally documented material. Contents 1. Matrox Solios with MIL. 1.1 What’s new 1.1.1 Differences between MIL 8.0 Update 8 and MIL 8.0 Update 5 1.1.2 Differences between MIL 8.0 Update 5 and MIL 8.0 1.2 Limitations and particularities. 1.3 Last minute information. 2. Matrox Solios with ActiveMIL. 3. Matrox Solios Installation and Hardware Reference manual. 3.1 Errors and omissions. 4. Processing FPGA documentation. 1. Matrox Solios with MIL. 1.1 What’s new 1.1.1 Differences between MIL 8.0 Update 8 and MIL 8.0 Update 5 - MIL includes the following PUs and now supportes them using MIL functions: - The gainoffset PU. Performs the same functionality as MimArithMultiple with M_OFFSET_GAIN. - The addconst PU. Performs the same functionality as MimArith with M_ADD_CONST. - The bayer PU. Performs the same functionality as MbufBayer. - The lutmap PU. Performs the same functionality as MimLutMap. - The minmax PU. Performs the same functionality as MimFindExtreme. - The rgb2hsl PU. Performs the same functionality as MimConvert with M_RGB_TO_HSL. - The planeseparator PU. Converts a packed stream or buffer to a planar format. - The splitter PU. Duplicate an input stream. - A new Mfpga low-level API is now supported. - New board specific examples that demonstrate the use of the Processing FPGA using standard MIL calls (installed in the Matrox Imaging\Mil\Examples\board-specific\solios folder). - New examples that demonstrate the Mfpga API (installed in the Matrox Imaging\Mil\Examples\SoliosFDK folder). - A new tool called Matrox FPGA assistant (installed in the Matrox Imaging\tools folder). - New Processing FPGA configurations (installed in the Matrox Imaging\Drivers\Solios\Firmware\processing folder). - A Processing FPGA tab was added to the MilConfig utility. With this tab, you can select the Processing FPGA configuration to load during system allocation. - Improved firmware update support. - New acquisition FPGA firmware (installed in the Matrox Imaging\Drivers\Solios\Firmware folder). 1.1.2 Differences between MIL 8.0 Update 5 and MIL 8.0 - Silent redistribution of driver update is now functional. - Implemented a cleaner recovery mechanism for FLASH configuration corruption that can occur on 66MHz Camera Link boards. - Added support for Processing FPGA option - Released FPGA configuration file solios_pf_0001_EP1S30C7 that implements Bayer filter, gain and offset correction and add-a- constant functions. - Released sample examples that offloads processing on the FPGA. See AddConstant.c and ProcessingFpga.c examples in folder Mil\Examples\Board-Specific\Solios. - Created new buffer attributes to target the memory bank to use during buffer allocation. - M_GRAB+M_FPGA_MEMORY allocates a buffer in the Grab FPGA SDRAM memory bank (M_MEMORY_BANK_0). - M_GRAB+M_PROC+M_FPGA_MEMORY allocates a buffer in the Grab FPGA SDRAM memory bank (M_MEMORY_BANK_0). - M_PROC+M_FPGA_MEMORY allocates a buffer in the Processing FPGA SDRAM memory bank (M_MEMORY_BANK_1). - M_PROC+M_FPGA_MEMORY+M_FAST_MEMORY allocates a buffer in the Processing FPGA SRAM memory bank (M_MEMORY_BANK_2). Note: M_FAST_MEMORY (M_MEMORY_BANK2) is not supported in this release. - The following table lists the source and destination buffer location for processing to be offloaded: ______________________________________________________ | | Buffer location | | |________________________________________| | | Source buffer(s) | Destination buffer | |_____________|___________________|____________________| | Bayer | M_MEMORY_BANK_0, | M_MEMORY_BANK_0, | | | M_MEMORY_BANK_1 | M_MEMORY_BANK_1, | | | | M_HOST_MEMORY | |_____________|___________________|____________________| | Gain&Offset | M_MEMORY_BANK_0 | M_MEMORY_BANK_1, | | | (See note) | M_HOST_MEMORY | |_____________|___________________|____________________| | AddConstant | M_MEMORY_BANK_0, | M_MEMORY_BANK_1, | | | M_MEMORY_BANK_1 | M_HOST_MEMORY | |_____________|___________________|____________________| Note: For Gain&Offset, the buffer to process must be in M_MEMORY_BANK_0, the gain and offset buffers must be in M_MEMORY_BANK_1. The destination can either be in M_MEMORY_BANK_1 or in M_HOST_MEMORY. - With the appropriate configuration loaded, the Processing FPGA will offload the following MIL API calls and under the following conditions (see examples\board-specific\solios folder for Processing FPGA examples AddConstant.c and ProcessingFpga.c): - MimArith (M_ADD_CONST): - Source buffer and destination buffer must have the same attributes and the same type - Valid types are 8+M_UNSIGNED or 8+M_SIGNED - Source and destination buffer sizes must be the same - Source and destination buffers must be packed for color buffers - Source must be M_FPGA_MEMORY+M_MEMORY_BANK_0 (Grab FPGA SDRAM memory) or M_FPGA_MEMORY+M_MEMORY_BANK_1 (processing FPGA SDRAM memory) - Destination must be M_FPGA_MEMORY+M_MEMORY_BANK_1 (processing SDRAM memory), or in Host non-paged memory. - M_SATURATION is supported and can be added to M_ADD_CONST - MbufBayer: - M_WHITE_BALANCE_CALCULATE is not supported by FPGA, M_WHITE_BALANCE_CALCULATE will be done by host (The FPGA can use pre-calculated white balancing coefficients). - Source buffer must be 1 band - Source and destination buffer sizes must be the same - Source and destination buffer SizeY must be an even number - Source and Destination must be 8+M_UNSIGNED (temporary limitation) - The color-space converter in the Grab FPGA will NOT be used if destination is M_BGR32+M_PACKED or M_BGR24+M_PACKED. Using color-space converter in the Grab FPGA reduces the performance of on-board processing (temporary limitation). - Source buffer must be M_FPGA_MEMORY+M_MEMORY_BANK_0 (Grab FPGA SDRAM memory) or M_FPGA_MEMORY+M_MEMORY_BANK_1 (processing FPGA SDRAM memory) - Destination buffer must be M_FPGA_MEMORY+M_MEMORY_BANK_1 (processing FPGA SDRAM memory), or in Host non-paged memory. - MimArithMultiple (M_OFFSET_GAIN): - All Source and destination buffer sizes must be the same - All source and destination buffer bands must be equal (all 1 band or all 3 band) - All source and destination buffers must be packed for color buffers - Source buffer 1 must be M_FPGA_MEMORY+M_MEMORY_BANK_0 (Grab FPGA SDRAM memory) - Source buffer 2 and 3 must be M_FPGA_MEMORY+M_MEMORY_BANK_1 (processing FPGA SDRAM memory) - Destination buffer must be M_FPGA_MEMORY+M_MEMORY_BANK_1 (processing FPGA SDRAM memory), or in Host non-paged memory. - The following buffer type combinations are supported by this release: Src type Offset type Gain type DstType U8 U8 U8 U8 - Source 4 must be a power of 2 (see MimArithMultiple M_OFFSET_GAIN in the MIL documentation). In all cases it is best to grab in M_MEMORY_BANK_0 and process from that source to a host non paged destination buffer. - Added M_GRAB_EXPOSURE_TRIGGER_MISSED parameter to MdigInquire() and MdigGetHookInfo() functions. - Added M_TRIGGER_FOR_FIRST_GRAB parameter to MdigProcess(). - Support for exposure clock source coming from AUX_IN. - Support for all rotary encoder modes. - Ability to inquire of the rotary encoder count on grab line. - Support for reversing grab direction (MdigControl/MdigInquire with M_GRAB_DIRECTION_X and M_GRAB_DIRECTION_Y). - Added capture-ignore mode (when enabled in the DCF). - Support for 85Mhz Camera Link acquisition speed. - Support for serial communication at up to 230Kbaud (with XCL version 1xx, eCL version 0xx and up). - Support for 10-bit RGB acquisition. - Bug fixes and other improvements: - Changing the configuration of an 85 MHz Camera Link board from dual-Base to single-Medium will no longer drop the maximum acquisition speed to 66 MHz. - Improved FPGA configuration update and board recognition process. - Fixed various DMA transfer bugs in the latest FPGA configuration. - Fixed a system crash (BSOD) that occurs when a target unit is set to null. - Removed a possible deadlock condition in the MdigProcess() function. - Increased the minimum grab timeout value from 1 to 5 seconds. - Fixed various software trigger issues. - Improved CC (camera control) bit behavior for Camera Link boards. - Fixed setting of the external I/O pins according to DCF. - Fixed a system crash (BSOD) that occurs when using a queued MdigLut() function. - Fixed data corruption with frame sizes bigger then 8K lines. - Fixed a dispatching problem with some MdigControl() calls. - Improved Timer settings and control, and fixed a Timer 2 programming error. - Fixed a problem with MdigFree() in a multi-digitizer configuration. - Fixed a system crash (BSOD) when no internal grab buffer is used. - Fixed an issue causing frame scan acquisition to lose sync. - Fixed a system crash (BSOD) that occurs when a halt command is called with no continuous grab started. - Fixed an issue in ThrControl() with M_TIMEOUT and MthrWait()(event and thread) functions. - Fixed a General Protection Fault (GPF) that occurs with a hook operation when an unhook operation occurs at the same time as a hook command is called. - Removed latency in MbufFree(). - Fixed a potential problem with buffer allocation and a minor issue with MbufInquire(). - Fixed an inquire value for SCAN_MODE. - Fixed a problem with slow scan cameras (for example, , acquisition below 12 MHz). - Removed a false error generated in Trigger source and Exposure source. - Fixed an issue with configuration bits when switching from Camera Link dual-Base to Medium or vice-versa. - Fixed a timeout problem with acquisition in trigger mode. 1.2 Limitations and particularities. - Processing FPGA - There is a known issue with aborts of the HSSI module in write mode (the destination buffer of the processing operation resides in M_MEMORY_BANK_0). The next operation involving an HSSI write will fail and the processing operation result will be incomplete. - This release requires a processing FPGA C5 speed-grade. - This release requires changing the processing FPGA core clock frequency. This will render the solios processing FPGA on the board incompatible with older versions of the solios driver and processing FPGA configuration. - All Buffer line length (M_SIZE_X) for FPGA processing must be a multiple of 64. - Processing in child buffers is not supported. - MimLutMap on the Solios Processing FPGA is limited to 8 bits for source, LUT and destination buffers. - MimLutMap on the Solios Processing FPGA is not thread safe. The wrong LUT might be applied if two threads issue a MimLutMap to the processing FPGA simultaneously. - To use MfpgaHookFunction/MfpgaGetHookInfo you must have made at least one prior call to MfpgaCommandAlloc (on any PU). - MimArithMultiple (with M_OFFSET_GAIN) always saturates the result image regardless of the M_SATURATION flag. - MbufCopy(): - The DMA transfer line count is limited to 4095 lines. If your buffer has more that 4095 linesYou must split your DMA transfers . - MdigGrab(): When grabbing in on-board buffers, the following limitations apply: - The buffer size-x and size-y must match the DCF. - The buffer type must match the DCF. When grabbing with a 10 or 12 bit camera in an on-board 8 bit buffer, some image data might be missing or improperly shifted depending on the DCF tap configuration. - MdigAlloc(): The mode of Matrox Solios can be changed through MILConfig (Solios tab) from its factory-default setting of single-Medium to dual-Base. Follow all on-screen procedures. Once changed, the PC must be shut-down and then turned back on (perform a cold-boot) for changes to take effect. Note that simply restarting your computer (using the Start Shut Down Windows Restart command) will not allow the changes to take affect. If you change the mode of Matrox Solios, make certain you also change your DCF. Using the wrong DCF when performing a digitizer allocation (using MdigAlloc()) will result in an error. - MdigChannel(): - Changing the synchronization channel with M_CHn+M_SYNC is not yet supported. - Processing FPGA: - M_FPGA_MEMORY+M_MEMORY_BANK_2 is not yet supported. - Buffer line length (pitch) must be a multiple of 64 bytes for the processing FPGA to work. - Processing of child buffers is not supported - Bayer processing is temporarily limited to 8 bit buffers. - MIL 64-bit: - Solios XA (7190-01) and Solios XCL (7184-00) are not supported in 64-bit OS. 1.3 Last minute information. - Msys...() additions: - MsysControl(M_UART_FREE+M_UART_NB(M_DEVn)): - This stops MIL UART operations and frees UART resources used by MIL. 2. Matrox Solios with ActiveMIL. - All the above information also applies to ActiveMIL. 3. Matrox Solios Installation and Hardware Reference manual. 3.1 Errors and omissions. - Before the synchronization and control signals table in the "Matrox Solios XA acquisition section and the Analog module" section of the "Frame grabbers" chapter, it states that TTL/LVDS signals can be set individually to either TTL or LVDS. This is incorrect. You can TTL/LVDS signals in pairs to either TTL or LVDS. - The mechanical dimensions stated for the Matrox Solios XCL and XA boards (6.6 X 4.2 X 0.68 inches) are for revision 0 of the boards. The dimensions for the following versions of the boards are: - Solios XCL (7184-01): 7.5 X 4.2 X 0.68 inches - Solios XA (7190-02): 9.225 X 4.2 X 0.68 inches 4. Processing FPGA documentation. - This documentation is available in the MILHelp.chm, under "MIL Readme Files". There is a user guide part ("Using MIL with a Processing FPGA") and a reference part ("Mfpga reference").